Computer Structure
0368-2159
Semester I, 2003-4
Lecturers: Yehuda Afek <afek@cs.tau.ac.il>, Yossi
Matias
<matias@cs.tau.ac.il>
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Teaching Assistant: Alon Schclar <shekler@cs.tau.ac.il>
Announcements
Exam on
Friday, February 20:
· The exam will be with open
material. Electronic devices are not allowed
· Material includes all that was
covered in classes and in the Tirgulim, including
class on the Intel architecture (slides marked as “material for exam b&w”)
· Good luck!
Suggested Books
· For the first part of the course: V. C. Hamacher, Z. G. Vranesic, S. G. Zaky Computer
Organization. McGraw-Hill, 1982
· For the second part of the course: Patterson
Hennessy Computer
Organization Design, The Hardware/Software Interface. Morgan Kaufmann,
1998 Slides
· Older course book for the first part of the
course: H. Taub Digital
Circuits and Microprocessors. McGraw-Hill, 1982
Course outline (tentative)
· Introduction
An introduction to the course,
What is it Computer Structure?
The importance of Instruction sets
Memory hierarchies
Technological forces driving computer
structure
Silicon -> Transistors ->
logical gates
Implementing basic logical circuits from CMOS transistors
.
Representation
of numbers
Binary, Octal and Hexadecimal number systems
Bases
transfer of integers and fractions
The
one's complement and two's complement
Representation of
signed numbers
·
Algebra
of logical variables
Logical
variables and functions
The OR, AND, NOT functions
Boolean Algebra Theorems
De'Morgan's Theorem
The XOR, NAND and NOR functions
Universal System
· Karnaugh Maps, Combinatorial Circuits
Simplification of
Logical functions using Boolean Algebra Theorems
Simplification using Karnaugh Maps
Circuit implementation
The Don't care utility for function minimization
· Basic Logic Building Blocks (Mux, Decoder)
Decoders and Encoders (mux)
· Flip
Flops
A
latch with NAND gates
The need for latch and synchronization
Clocked FF
Truth table and timing diagram for a FF
Two phase clocking and
the Master/Slave RS FF
The JK FF, D and T flip-flops
Shift registers
· Registers,
Counters
Serial, parallel
Serial implementation of a full adder
Counters
·
Finite State
Machines
The state and transition diagrams
Mealy and Moore
Elimination of redundant states
·
The
RISC Instruction Set and Assembly Language
The MIPS R2000 Assembly Language
Instructions' representation in the computer
Addressing modes
Compiler, linker, loader
RISC vs. CISC
· Compiler, linker, loader
·
Single Cycle Architecture
Execution phases
Building a CPU from basic components
A
simple implementation scheme: datapath and control
The problems of single cycle.
·
Multi Cycle Architecture
Implementation
Control unit
· Multi-Cycle Control Unit
Flip-Flops review,
PLA
Microprogramming
Exceptions and Interrupts