School of Computer Science

Computer Structure

0368-2159-07

Semester II, 2002

Prof. Yossi Matias

Teaching Assistant: Dror Irony

TIRGUL Homepage

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Announcements

· [NEW] The exams (both moed A & B) will be with open material

· [NEW] Moed Beit will cover the same material as Moed Alef

· Example solutions to exercises are available at the Tirgul homepage.

· Exercise on multicycle architecture (5) is optional – students are encouraged to solve.

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Suggested Books

· For the first part of the course:  V. C. Hamacher, Z. G. Vranesic, S. G. Zaky Computer Organization. McGraw-Hill, 1982

· For the second part of the course:  Patterson Hennessy  Computer Organization Design, The Hardware/Software Interface. Morgan Kaufmann, 1998     Slides

· Older course book for the first part of the course:  H. Taub  Digital Circuits and Microprocessors. McGraw-Hill, 1982

Course outline

(Online material courtesy of Prof. Nathan Interator and Dr. Anat Bremler-Bar)

· Algebra of logical variables Introduction Notes1 Notes2 (html)

                    Logical variables and functions
                    The OR, AND, NOT functions
                    Binary, Octal and Hexadecimal number systems
                    Bases transfer of integers and fractions
                    The one's complement and two's complement
                    Representation of signed numbers
                    Boolean Algebra Theorems
                    De'Morgan's Theorem
                    The XOR, NAND and NOR functions
                    Universal System

· Basic Logic Building Blocks (Mux, Decoder) FlipFlops (html)

                    Binary Representations: Sum of products and products of sums
                    Decoders and Encoders (mux)
                    A latch with NAND gates
                    The need for latch and synchronization
                    Clocked FF
                    Truth table and timing diagram for a FF
The JK FF, D and T flip-flops

· Registers Counters (html)

                    Shift registers
Serial to parallel
                    Parallel to serial
                    Serial implementation of a full adder
                    Counters and dividers
Ripple counter and a synchronous counter (html)
                    Non-binary counters

· Karnaugh Maps (html)

                    Simplification of Logical functions using Boolean Algebra Theorems
                    Simplification using Karnaugh Maps
                    Circuit implementation
                    The Don't care utility for function minimization
                    Internal, external and input states

· Finite state machine (FSM) Sequential Circuits (html)

                    The state and transition diagrams
                    Mealy circuits
                    A sequence detector
                    Elimination of redundant states
                    Implementation of an Up-down counter with a FSM

· The RISC Instruction Set and Assembly Language (ppt)

                    The MIPS R2000 Assembly Language
                    Instructions' representation in the computer
                    Addressing modes
                    Compiler, linker, loader
                    RISC vs. CISC

· Single Cycle Architecture (ppt)

                    Execution phases
                    Building a CPU from basic components
A simple implementation scheme: datapath and control
                    The problems of single cycle.

· Multi Cycle Architecture (ppt)

                    Implementation
                    Control unit

· Pipelined Architecture (ppt)

                    Pipelined datapath
                    Pipelined control

·          Pipelined Architecture - Hazards resolution

                    Hazards detection and resolution
                    Nops and bubbles
                    Forwarding
                    Branch hazards

· Cache (ppt)

Past Exams (MS Word 97 format)

Oct 14, 1998 Dec 18, 1998

Mar 17, 1999 Jun 30, 1999

Oct 13, 1999 Dec 17, 1999

Additional material:

Advanced computer periferals

DSP Introduction

Components: 74xx TTL Family Links Software

CPU: Risc CPU Tech Sheets   History

WWW Computer Architecture Page

Contact:

Prof. Yossi Matias – matias+csc02@cs.tau.ac.il

Dror Irony – irony@tau.ac.il