Computer Structure
מבנה מחשבים
0368-2159-05
Instructor:
|
Nathan Intrator
|
Wed
2-5
|
Dach 05
|
nin@ tau.ac.il
|
|
TA: |
Kiril Solovey |
Sun 3-4 |
Orens. 111 |
kirilsolo@gmail.com |
|
|
Sun
4-5 |
Orens.
111 |
||
|
|
|
Thu
2-3 |
Soft Eng. 104 |
|
Administration & Messages
TARGILIM
(homework) Homework grade calculation: To get
the full grade on the homework you have to submit **ALL** the exercises. The homework grade will be the average of all
of them.
Moodle site: http://moodle.tau.ac.il
Prof. Eytan Ruppin’s site: http://www.cs.tau.ac.il/~ruppin/mivne.html
Test:
i) Jun 26, 2013, ii) Aug 9, 2013
News
and Updates
Core I7 from Intel 300 TByte Disk New Core Duo
AMD Quad Core AMD Triple Core End of Pentium 4
Suggested
Books
·
Course summary and past tests can be found on
the students page
·
For the first part of the course: V. C. Hamacher, Z. G. Vranesic, S. G. Zaky Computer Organization. McGraw-Hill,
1982
- H. Taub Digital
Circuits and Microporcessors. McGraw-Hill 1982
·
An introductory book about VHDL such as: VHDL Cook Book, Ref Manual See also VHDL Archive
·
For the second part of the course:
Patterson Hennessy Computer Organization Design, The Hardware/Software
Interface. Morgan Kaufmann, 1998 Slides
·
Older course book for the first part of the
course: H. Taub
·
Digital Circuits and
Microprocessors. McGraw-Hill, 1982
Grades:
·
Final Exam 80%
·
Exercises 20% (7 exercises)
Course Outline (Some
changes from last year will follow):
Full
set of lectures of Limor (Sem A
2007-8) Video Recordings
1.
Introduction Scribe2 Exercice
Classes 2006
a. An introduction to
the course
b. What is it Computer
Structure?
c.
The importance of
Instruction sets
d. Memory hierarchies
e. Technological
forces driving computer structure
f.
Silicon -> Transistors -> logical gates
g. Implementing basic
logical circuits from CMOS transistors
h. Java applets simulating CMOS transistor
implementations of digital logic gates see also second demo
i.
Ray Kurzweil Brain/Computer Future
2. Representation of numbers Scribe1 Scribe2 Shirly_Scribe
a. Binary, Octal and
Hexadecimal number systems
b. Bases transfer of
integers and fractions
c. The one's
complement and two's complement
d. Representation of
signed numbers
3. Algebra of logical variables Shirly_Scribe
a.
Logical variables and functions
b.
The OR,
AND, NOT functions
c.
Boolean Algebra
Theorems
d.
De'Morgan's Theorem
e.
The XOR, NAND and NOR functions
4.
Universal System
Karnaugh Maps, Combinatorial Circuits PDF
Shirly_Scribe Limor_Scribe Michal_Scribe
a. Simplification of Logical functions using Boolean Algebra Theorems
b. Simplification
using Karnaugh Maps
c. Circuit
implementation
d. The Don't care utility for function minimization
5. Basic Logic Building Blocks (Mux, Decoder) PDF
a. Decoders and Encoders (mux)
b. Introduction to VHDL
6. Flip Flops Scribe
Shirly Scribe
Michal
a. A latch with NAND
gates
b. The need for latch
and synchronization
c. Clocked FF
d. Truth table and
timing diagram for a FF
e. Two phase clocking
and the Master/Slave RS FF
f.
The JK FF, D and T flip-flops
g. Shift
registers
7. Registers, Counters, Simplification of Logical
Functions Scribe
Michal
Shirly_Scribe
a. Serial to parallel
b. Parallel to serial
c. Serial
implementation of a full adder
d. Counters and
dividers
e. Ripple counter and
a synchronous counter
f.
Non-binary counters
g. Analog to
Digital Conversion
8. VHDL Quick Primer and
Fundamental DSP + FSM Scribe
Michal Shirly_Scribe
a. VHDL
Introduction to VHDL Tutorial Ref Manual
b. Sequential Circuits (FSM)
c. The state and
transition diagrams
d. Mealy circuits
e. A sequence detector
f.
Elimination of redundant states
g. Review VHDL
9. The
RISC Instruction Set and Assembly Language Shirly_Scribe
a. The MIPS R2000
Assembly Language
MIPS Instruction Set Architecture (ISA) Spec
MIPS Instruction Reference
RISC vs. CISC
b. Instructions'
representation in the computer
c. Addressing modes
d. Compiler, linker, loader
e. RISC vs. CISC
10. Single Cycle Architecture Scribe
Michal Shirly_Scribe
a. Execution phases
b. Building a CPU from basic components
c. A simple implementation scheme: data path and
control
d. The problems of single cycle.
11. Pipelined
Architecture Scribe
Michal Shirly_Scribe
a. Pipelined datapath
b. Pipelined control
c. Pipelined
Architecture - Hazards detection and resolution
d. Nops and bubbles
e. Forwarding
f.
Branch hazards
12. Cache Scribe
Michal
a. Branch Prediction
b. Supplementary
material:
13. Multi
Cycle Architecture
a. Implementation
b. Control unit
14. Multi-Cycle
Control Unit
a. Flip-Flops review
b.
Finite State Machine Design, Moore and Mealy,
c.
PLA, ROM
d.
Microprogramming,
Exceptions and Interrupts