Computer Structure

מבנה מחשבים





Nathan Intrator

Wed  2-5

Dach 05



Kiril Solovey

Sun  3-4

Orens. 111


Sun  4-5

Orens. 111



Thu  2-3

Soft Eng. 104




Administration & Messages

Mailing List     Yedion


TARGILIM (homework) Homework grade calculation: To get the full grade on the homework you have to submit **ALL** the exercises.  The homework grade will be the average of all of them.


Moodle site:                    

Prof.  Eytan Ruppin’s site:


Test:   i) Jun 26, 2013,   ii) Aug 9, 2013


News and Updates

Core I7 from Intel            300 TByte Disk                   New Core Duo

 AMD Quad Core           AMD Triple Core                  End of Pentium 4


Suggested Books

·         Course summary and past tests can be found on the students page

·         For the first part of the course:  V. C. Hamacher, Z. G. Vranesic, S. G. Zaky Computer Organization. McGraw-Hill, 1982

·         An introductory book about VHDL such as: VHDL Cook Book, Ref Manual  See also VHDL Archive

·         For the second part of the course:  Patterson Hennessy  Computer Organization Design, The Hardware/Software Interface. Morgan Kaufmann, 1998     Slides

·         Older course book for the first part of the course:  H. Taub 

·         Digital Circuits and Microprocessors. McGraw-Hill, 1982



·         Final Exam 80%

·         Exercises 20% (7 exercises)


Course Outline (Some changes from last year will follow):

Full set of lectures of Limor (Sem A 2007-8)    Video Recordings


1.       Introduction          Scribe2                  Exercice Classes 2006

a.       An introduction to the course

b.      What is it Computer Structure?

c.       The importance of Instruction sets

d.      Memory hierarchies

e.      Technological forces driving computer structure

f.        Silicon -> Transistors -> logical gates

g.       Implementing basic logical circuits from CMOS transistors

h.       Java applets simulating CMOS transistor implementations of digital logic gates see also second demo

i.         Ray Kurzweil Brain/Computer Future


2.       Representation of numbers               Scribe1                 Scribe2  Shirly_Scribe

a.       Binary, Octal and Hexadecimal number systems

b.      Bases transfer of integers and fractions

c.       The one's complement and two's complement

d.      Representation of signed numbers


3.       Algebra of logical variables                                Shirly_Scribe

a.       Logical variables and functions

b.       The OR, AND, NOT functions

c.       Boolean Algebra Theorems

d.      De'Morgan's Theorem

e.      The XOR, NAND and NOR functions


4.       Universal System
Karnaugh Maps, Combinatorial Circuits     PDF    Shirly_Scribe  Limor_Scribe   Michal_Scribe

a.       Simplification of Logical functions using Boolean Algebra Theorems

b.      Simplification using Karnaugh Maps

c.       Circuit implementation

d.      The Don't care utility for function minimization


5.       Basic Logic Building Blocks (Mux, Decoder)      PDF

a.       Decoders and Encoders (mux)

b.      Introduction to VHDL 


6.       Flip Flops               Scribe Shirly          Scribe Michal       

a.       A latch with NAND gates

b.      The need for latch and synchronization

c.       Clocked FF

d.      Truth table and timing diagram for a FF

e.      Two phase clocking and the Master/Slave RS FF

f.        The JK FF, D and T flip-flops

g.       Shift registers 


7.        Registers, Counters, Simplification of Logical Functions  Scribe Michal    Shirly_Scribe

a.       Serial to parallel

b.      Parallel to serial

c.       Serial implementation of a full adder

d.      Counters and dividers

e.      Ripple counter and a synchronous counter

f.        Non-binary counters

g.       Analog to Digital Conversion


8.       VHDL Quick Primer  and Fundamental DSP + FSM  Scribe Michal   Shirly_Scribe

a.       VHDL   Introduction to VHDL     Tutorial   Ref Manual

b.      Sequential Circuits    (FSM)

c.       The state and transition diagrams

d.      Mealy circuits

e.      A sequence detector

f.        Elimination of redundant states

g.       Review VHDL


9.       The RISC Instruction Set and Assembly Language                          Shirly_Scribe

a.       The MIPS R2000 Assembly Language   

MIPS Instruction Set Architecture (ISA) Spec

MIPS Instruction Reference      


b.      Instructions' representation in the computer

c.       Addressing modes

d.       Compiler, linker, loader

e.      RISC vs. CISC


10.    Single Cycle Architecture                   Scribe Michal                        Shirly_Scribe

a.       Execution phases

b.      Building a CPU from basic components

c.        A simple implementation scheme: data path and control

d.       The problems of single cycle.


11.    Pipelined Architecture                       Scribe Michal                        Shirly_Scribe

a.       Pipelined datapath

b.      Pipelined control

c.       Pipelined Architecture - Hazards detection and    resolution

d.      Nops and bubbles

e.      Forwarding

f.        Branch hazards

12.     Cache                                    Scribe Michal

a.       Branch Prediction

b.      Supplementary material:


13.     Multi Cycle Architecture    

a.       Implementation

b.      Control unit


14.    Multi-Cycle Control Unit

                        a.      Flip-Flops review

                         b.      Finite State Machine Design, Moore and Mealy,

                          c.      PLA, ROM

                        d.      Microprogramming,  Exceptions and Interrupts

Past Exams

The following exams do not necessarily indicate what questions will be in this year exam. 

In addition or instead of the traditional questions there will be questions on:

·         Transistors

·         A/D

2009-A   2007-8 Sem A (with Solution)

2005AB  2005A   2005C

2004 A    2003 A  2003 B

Dec 18, 1998

Mar 17, 1999    Jun 30, 1999  (note corrections is Questions 1& 2)

Oct 13, 1999    Dec 17, 1999

Solutions for the Exam from Feb 25:  Full Exam, Quest 2, Quest 1,5



*Note that the material of the course has changed recently, so older exams (before 1998) do not reflect the full material of the course. The exams are in word 97 format.

*(Note that since last year VHDL has been added and is an integral part of the course.


  Additional material:

Advanced computer periferals

DSP Introduction

Components: 74xx TTL Family  Links  Software

CPU: Risc CPU Tech Sheets    History

WWW Computer Architecture Page 


Past guest talks:

The Pentium(r) II/III Processor - Compiler on a Chip (PDF),

In this lecture we will give a brief overview of the ingredients of modern processor micro-architecture in general and will describe its usage in the Intel Pentium II/III processor family.  As time permits, we will discuss the aspects of power and energy in novel processors and will show how it is reflected in the new Intel Pentium M Processor.

Ronny Ronen is a Senior Principal Engineer/Researcher and the director of the Intel's Microprocessor Research Lab in Haifa, Israel, focusing on microarchitecture research.  Ronny was heavily involved in the definition stages of the Intel Pentium M processor.  He has been with Intel for 22 years.  Earlier in Intel he led the compiler and performance simulation activities in the Intel Israel Software department.  Ronny received his M.Sc. degree from the Technion, Israel Institute of Technology in 1979.  Modern Intel     Only relevant slides in Black & White version   and   Pentium M

Intel Prescott chip